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The Silicon Computing Development Organization is seeking engaged, committed and intellectually curious engineers to join our pre-silicon hardware verification team. We are responsible for delivering cutting-edge, custom System-On-Chip (SOC) designs that can perform complex and high-performance functions in the most efficient manner.
Open to 100% remote in the U.S.
- Own or lead verification of one or more aspects/features of a memory controller Intellectual Property (IP) and/or Double Data Rate (DDR)subsystem integration
- Learn about the design and interact with partner teams to define verification strategies and test plans
- Developverification environments that run and debug simulations to drive quality
- Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
- Innovate to improve verification efficiency through methodologies or tools
- Coach and mentor others in your areas of expertise
- Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion
Required/Minimum Qualifications:
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9+ years of related technical engineering experience
o OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
o OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
o OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
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8+ years of pre-silicon SOC or IP verification experience with 4+ years ofexperience using the industry standard JEDEC specification to verify DDR controller IP and/or sub-system with DDR controller and Physical Layer (PHY)
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Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check every two years thereafter.
Preferred Qualifications:
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15+ years technical engineering experience
o OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience
o OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
o OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience.
- Solid background and understanding of memory subsystem architectures and principles with related experience.
- Deep understanding of JEDEC spec including mode registers, timing parameters, refresh operations, initialization, calibration, training, power management, and error handling.
- Sub-system level experience including integration verification of DDR PHY with memory controller IP and Electronic Design Automation (EDA) vendor sourced Dual In-line Memory Module (DIMM) Verification IP (VIP)
- Demonstrated hands-on technical leadership such as creating bottom’s up schedules, coordinating work across a team, driving verification closure, or solving cross-team technical problems
- Experience creating, maintaining, or integrating test benches, checkers and stimulus using System Verilog Test Bench (SVTB), Universal Verification Methodology (UVM) and/or C
- Aptitude for writing scripts/software with industry standard languages like Python
- Knowledge and/or experience in additional areas such as:
- Experience verifying memory Reliability, Availability, and Serviceability (RAS) features
- Experience with performance and/or power verification of a memory controller design
- Hands-on experience with debugging post-silicon failures in a labsetting
- Experience driving IP verification for multiple product cycles from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff
Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $133,600 - $256,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $173,200 - $282,200 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form.
Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.
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